1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly, to a bilayer silicon carbide (SiC) barrier for interconnect metallization applications.
2. Description of the Prior Art
As a demand for faster device speeds continues to increase, fabrication and design engineers have been implementing lower dielectric constant materials. Typically, the speed of an interconnect structure is characterized in terms of RC (resistance/capacitance) delays. The lower dielectric constant materials help in reducing inter-metal capacitance, and therefore, reduce RC delays and improve device speeds.
Dual damascene processes are world widely used interconnect metallization techniques applying in high-speed logic devices of design rules below 0.25 micrometers. In dual-damascene applications, interconnect metallization lines are formed in trenches of dielectric layers and are formed of copper (Cu). In addition to the interconnect metallization lines, the dual-damascene structures further comprises via plugs to electrically connect the metallization lines with other conductive layers. As known to those skilled in the art, the conventional dual damascene techniques include: (1) a via-first process, (2) a self-aligned process, and (3) a trench-first process.
No matter which fabrication process of the above-mentioned dual damascene techniques is chosen, a barrier layer is finally deposited on the metal layer filling in the trench. The barrier layer is used to prevent outward migration of metals and prevent oxidation of metals. Normally, silicon nitride is used to form the barrier layer. However, silicon nitride has a great dielectric constant ( greater than 6.5) and thus reduces operating speeds of the interconnect metallization lines. In order to improve the operating speeds of the interconnection metallization lines, Furumura et al. (U.S. Pat. No. 5,103,285) use silicon carbide (SiC) to form a barrier layer between a silicon substrate and a metal wire, the SiC barrier layer having a low dielectric constant of about 4-5. Mark et al. (U.S. Pat. No. 5,818,071) use amorphous SiC (a-SiC) to form a barrier layer between a metal wire and a dielectric layer, preventing diffusion of metal atoms from the metal wire to the dielectric layer.
The SiC barrier layer has a lower dielectric constant compared to the conventional silicon nitride barrier layer, however, the SiC barrier layer still has some disadvantages, such as (1) low breakdown voltages, (2) high leakage currents, and (3) unstable film properties. Therefore, using low dielectric constant materials to form a barrier layer and simultaneously prevent the above-mentioned problems has become an important issue.
It is therefore an objective of the present invention to provide an interconnect metallization line with high performance and high reliability.
It is another objective of the present invention to provide a bilayer SiC-based barrier layer to prevent the above-mentioned problems.
An integrated circuit of the present invention substantially includes at least one metallic wiring layer damascened on a first dielectric layer, a bilayer SiC-based barrier deposited over the metallic wiring layer and the first dielectric layer, and a second dielectric layer formed over the bilayer SiC-based barrier.
The bilayer SiC-based barrier has a nitrogen-doped SiC bottom layer and an oxygen-doped SiC top layer formed by an in-situ deposition over the nitrogen-doped SiC bottom layer. The nitrogen-doped SiC bottom layer has a minimum thickness to prevent metal atoms of the metallic wiring layer from diffusing to the second dielectric layer and, at the same time, avoid oxygen atoms of the oxygen-doped SiC top layer from diffusing into the metallic wiring layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the multiple figures and drawings.